论文标题
用于对称电路加密的有限状态机的硬件水印
Hardware Watermarking for Finite State Machines, with Symmetric Circuit Encryption
论文作者
论文摘要
将水印置于数字电路中，有自己的一系列挑战。在印刷物质中创建安全的水印通常涉及包括难以复制的图形。在电路中，包括难以生产的其他电路，必须与增加电路功率消耗，降低电路速度并引入易于复制的水印电路的前景。在本文中，我们提出了一种用于顺序电路的水印方法。它允许进行几个程度的校准，从而使用户可以将水印的复杂性调整为速度，功率和功效的要求。我们的方法使用一种加密技术在几个层面上介绍有关水印电路的秘密。它还采用边界扫描测试协议作为保护水印电路的一种手段。我们的讨论首先描述我们水印方案中所需的不同工具。然后，我们讨论与打破水印电路有关的问题的困难。该分析表明，通过完整实施，我们的方法可以变得非常安全。
Putting a watermark into digital circuitry has its own set of challenges. Creating a secure watermark in printed matter usually involves including graphics that are difficult to reproduce. In circuitry, including additional circuitry that is hard to produce, one must contend with the prospect of increasing power consumption of the circuit, decreasing the speed of the circuit, and introducing watermark circuitry that is easily reproduced. In this paper we present a watermark method for sequential circuitry. It allows for several degrees of calibration, allowing the user to tune the complexity of the watermark to requirements of speed, power, and efficacy. Our method uses an encryption technique to introduce secrets about the watermark circuit, at several levels. It also employs a boundary scan testing protocol as a means to protect the watermark circuitry. Our discussion starts by describing the different tools needed in our watermark scheme. We then discuss the difficulty of the problem associated with cracking our watermark circuit. This analysis shows that, with full implementation, our method can be made quite secure.
